Toshiba Announces Energy-Saving Flip-Flop Circuit

February 21, 2011 by | Comments
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Toshiba Corporation announced that it has created a new flip-flop circuit using 40nm CMOS process that will lower power consumption in mobile equipment.

Tests carried out by Toshiba showed that the power dissipation of the new flip-flop is up to 77% less than that of a typical conventional flip-flop and that it reaches a 24% reduction in total power consumption when applied to a wireless LAN chip.

This achievement will be announced on February 23  at the 2011 IEEE International Solid-State Circuits Conference (ISSCC) now being held in the United States.

The circuit configuration of new technique

–(Toshiba Corporation News Releases)–

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